The present invention relates to the deposition of dielectric layers in wafer processing during the manufacture of an integrated circuit. More specifically, the present invention relates to a method and apparatus for forming a conformal silicon oxide thin film over a stepped or non-planar surface of a semiconductor wafer or substrate.
Interconnections on semiconductor devices are typically made by metal conductors, which in some cases are narrow, closely spaced metal lines. The use of two or more levels of metal conductors requires the need for a deposition of an insulating layer between the layers of metal to avoid a short circuit between conductors or another anomalies.
Thus, one of the primary steps in the fabrication of modern multilevel semiconductor devices is the formation of these insulating layers, which are also referred to as intermetal dielectric layers, or IMD layers. One of the primary methods of forming IMD layers on a semiconductor substrate is by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition or "CVD". Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having metal layers. Plasma enhanced CVD (frequently referred to as PECVD) processes on the other hand, promote excitation and/or dissociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone typically proximate the substrate surface, thereby creating a plasma of highly-reactive species. The high reactivity of the released species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such CVD processes. The relatively low temperature of a PECVD process makes such processes ideal for the formation of insulating layers over deposited metal conductors. SiO.sub.2 is a common IMD layer.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called "Moore's Law") which means that the number of devices which will fit on a chip doubles every two years. Today's wafer as fabrication plants are routinely producing 0.5 and even 0.35 micron feature size devices, and tomorrow's plants soon will be producing devices having even smaller geometries.
As circuit densities increase, the spacing between adjacent metal conductors decreases, which causes an increase in the ratio of the height of adjacent conductors to their separation, commonly referred to as the aspect ratio. An increase in the aspect ratio is accompanied by an increase in the likelihood that a deposited insulating layer will not conform to and completely fill the gap between conductors. Thus, as an insulating layer is deposited, an undesirable void may form within the layer between adjacent conductors. A void can form when the deposits on the upper portion of adjacent metal vertical side walls contact each other before the bottorm of the gap fills in.
One solution to this problem has involved depositing SiO.sub.2 derived from a precursor gas containing tetraethoxysilane (TEOS) (Si(OC.sub.2 H.sub.5).sub.4). An SiO.sub.2 layer formed from TEOS is referred to hereinafter as a TEOS deposition or insulating layer.
Another solution has been, instead of depositing an SiO.sub.2 insulating layer formed from TEOS, to deposit fluorine-doped silicon oxide films, which are also referred to as fluoro silicate glass films (FSG). Because fluorine is an etching species, fluorine doping introduces a simultaneous deposition/etch effect, where excess deposition layer is etched away, improving the gap fill. The simultaneous etch slows the deposition on the top of the sidewalls, so that the bottom of the gap can fill more before the top closes off.
Another solution has been, rather than performing a one-step deposition of an insulating layer between metal conductors, to perform a three-step process of TEOS deposition/etchback/TEOS deposition. In this three-step process, a TEOS insulating layer is partially deposited over a metal layer. Then, an etchback step is performed that etches away some of the excess silicon oxide that might cause an uneven deposition of further oxide layers, leading to void formation. The etchback removes some of the deposits at the top of the gap, keeping it from closing off too soon. Finally, the TEOS deposition is completed in the third step. The three step TEOS deposition/etchback/TEOS deposition process provides gap fill capabilities that are an improvement over performance of the one step TEOS deposition process.
With the shrinking semiconductor device sizes, as noted above, the gap widths between adjacent conductors are falling to below 0.5 micron. Thus, it would therefore be desirable to be able to deposit an insulating layer over a metal layer that has an gap fill capability for a higher aspect ratio, such as 2.0, for example.